HD6413008VF25 Datasheet, PDF (48/688 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

1. Overview
Table 1.1 Features
Feature
CPU
Memory
Interrupt
controller
Bus controller
Description
Upward-compatible with the H8/300 CPU at the object-code level
General-register machine
• Sixteen 16-bit general registers
(also usable as sixteen 8-bit registers plus eight 16-bit registers, or as eight
32-bit registers)
High-speed operation
• Maximum clock rate: 25 MHz
• Add/subtract: 80 ns
• Multiply/divide: 560 ns
16-Mbyte address space
Instruction features
• 8/16/32-bit data transfer, arithmetic, and logic instructions
• Signed and unsigned multiply instructions (8 bits × 8 bits, 16 bits × 16 bits)
• Signed and unsigned divide instructions (16 bits ÷ 8 bits, 32 bits ÷ 16 bits)
• Bit accumulator function
Bit manipulation instructions with register-indirect specification of bit positions
H8/3008
• RAM: 4 kbytes
•
Seven
external
interrupt
pins:
NMI,
IRQ
0
to
IRQ
5
• 27 internal interrupts
• Three selectable interrupt priority levels
• Address space can be partitioned into eight areas, with independent bus
specifications in each area
• Chip select output available for areas 0 to 7
• 8-bit access or 16-bit access selectable for each area
• Two-state or three-state access selectable for each area
• Selection of two wait modes
• Number of program wait states selectable for each area
• Bus arbitration function
• Two address update modes
Rev.4.00 Aug. 20, 2007 Page 2 of 638
REJ09B0395-0400