HD6413008VF25 Datasheet, PDF (172/688 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

6. Bus Controller
8-Bit, Two-State-Access Areas: Figure 6.10 shows the timing of bus control signals for an 8-bit,
two-state-access area. The upper data bus (D₁₅ to D₈) is used in accesses to these areas. The LWR
pin is always high. Wait states cannot be inserted.
Bus cycle
T1
T2
φ
Address bus
External address in area n
CSn
AS
RD
Read access D15 to D8
D7 to D0
HWR
Write access
LWR
D15 to D8
D7 to D0
Valid
Invalid
High
Valid
Undetermined data
Note: n = 7 to 0
Figure 6.10 Bus Control Signal Timing for 8-Bit, Two-State-Access Area
Rev.4.00 Aug. 20, 2007 Page 126 of 638
REJ09B0395-0400