HD6413008VF25 Datasheet, PDF (465/688 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

14. A/D Converter
Bit 7—Trigger Enable (TRGE): Enables or disables starting of A/D conversion by an external
trigger or 8-bit timer compare match.
Bit 7
TRGE
0
1
Description
Starting of A/D conversion by an external trigger or 8-bit timer
compare match is disabled
A/D conversion is started at the falling edge of the external trigger
signal (ADTRG) or by an 8-bit timer compare match
(Initial value)
External trigger pin and 8-bit timer selection is performed by the 8-bit timer. For details, see
section 9, 8-Bit Timers.
Bits 6 to 1—Reserved: These bits cannot be modified and are always read as 1.
Bit 0—Reserved: This bit can be read or written, but must not be set to 1.
14.3 CPU Interface
ADDRA to ADDRD are 16-bit registers, but they are connected to the CPU by an 8-bit data bus.
Therefore, although the upper byte can be be accessed directly by the CPU, the lower byte is read
through an 8-bit temporary register (TEMP).
An A/D data register is read as follows. When the upper byte is read, the upper-byte value is
transferred directly to the CPU and the lower-byte value is transferred into TEMP. Next, when the
lower byte is read, the TEMP contents are transferred to the CPU.
When reading an A/D data register, always read the upper byte before the lower byte. It is possible
to read only the upper byte, but if only the lower byte is read, incorrect data may be obtained.
Figure 14.2 shows the data flow for access to an A/D data register.
Rev.4.00 Aug. 20, 2007 Page 419 of 638
REJ09B0395-0400