English
Language : 

HD6413008VF25 Datasheet, PDF (210/688 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents
◁
7. I/O Ports
Port A Data Register (PADR): PADR is an 8-bit readable/writable register that stores output
data for port A. When port A functions as an output port, the value of this register is output. When
a bit in PADDR is set to 1, if port A is read the value of the corresponding PADR bit is returned.
When a bit in PADDR is cleared to 0, if port A is read the corresponding pin logic level is read.
Bit
Initial value
Read/Write
7
PA 7
0
R/W
6
PA 6
0
R/W
5
PA 5
0
R/W
4
PA 4
0
R/W
3
PA 3
0
R/W
2
PA 2
0
R/W
1
PA 1
0
R/W
0
PA 0
0
R/W
Port A data 7 to 0
These bits store data for port A pins
PADR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode it
retains its previous setting.
Rev.4.00 Aug. 20, 2007 Page 164 of 638
REJ09B0395-0400
 ▷