HD6413008VF25 Datasheet, PDF (95/688 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

2. CPU
Bus request
End of bus release
End of bus
Program execution state
release
Bus
request
Exception
Bus-released state
handling source
SLEEP
instruction
with SSBY = 0
Sleep mode
End of
exception
handling
Exception-handling state
Interrupt source
NMI, IRQ₀, IRQ ₁,
or IRQ ₂ interrupt
SLEEP instruction
with SSBY = 1
Software standby mode
RES = "High"
Reset state*¹
STBY = "High", RES = "Low"
Hardware standby mode*²
Power-down state
Notes: 1. From any state except hardware standby mode, a transition to the reset state occurs
whenever RES goes low.
2. From any state, a transition to hardware standby mode occurs when STBY goes low.
Figure 2.13 State Transitions
2.8.4 Exception Handling Operation
Reset Exception Handling: Reset exception handling has the highest priority. The reset state is
entered when the RES signal goes low. Reset exception handling starts after that, when RES
changes from low to high. When reset exception handling starts the CPU fetches a start address
from the exception vector table and starts program execution from that address. All interrupts,
including NMI, are disabled during the reset exception-handling sequence and immediately after it
ends.
Interrupt Exception Handling and Trap Instruction Exception Handling: When these
exception-handling sequences begin, the CPU references the stack pointer (ER7) and pushes the
program counter and condition code register on the stack. Next, if the UE bit in the system control
register (SYSCR) is set to 1, the CPU sets the I bit in the condition code register to 1. If the UE bit
is cleared to 0, the CPU sets both the I bit and the UI bit in the condition code register to 1. Then
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