HD6413008VF25 Datasheet, PDF (149/688 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

6. Bus Controller
6.1.3 Pin Configuration
Table 6.1 summarizes the input/output pins of the bus controller.
Table 6.1 Bus Controller Pins
Name
Chip select 0 to 7
Address strobe
Abbreviation
CS
0
to
CS
7
AS
I/O
Output
Output
Read
RD
Output
High write
HWR
Output
Low write
LWR
Output
Wait
WAIT
Bus request
BREQ
Bus acknowledge BACK
Input
Input
Output
Function
Strobe signals selecting areas 0 to 7
Strobe signal indicating valid address output
on the address bus
Strobe signal indicating reading from the
external address space
Strobe signal indicating writing to the external
address space, with valid data on the upper
data bus (D to D )
15
8
Strobe signal indicating writing to the external
address space, with valid data on the lower
data bus (D₇ to D₀)
Wait request signal for access to external
three-state access areas
Request signal for releasing the bus to an
external device
Acknowledge signal indicating release of the
bus to an external device
Rev.4.00 Aug. 20, 2007 Page 103 of 638
REJ09B0395-0400