HD6413008VF25 Datasheet, PDF (670/688 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Appendix D Pin States
Pin
Name
Hardware
Standby Software
Mode Reset Mode Standby Mode
Bus-
Program
Released Mode Execution Mode
PA
1, 2 T T
7
3, 4 L
T
PB₃ to PB₀ ⎯
T
T
Keep
(SSOE = 0)
T
(SSOE = 1)
Keep
(CS output)*³
(SSOE = 0)
T
(SSOE = 1)
H
(Otherwise)*⁴
Keep
Keep
T
I/O port
A
20
(CS output)*³
T
(Otherwise)*⁴
Keep
(CS output)*³
CS
7
to
CS
4
(Otherwise)*⁴
I/O port
PB to PB ⎯ T T
7
4
Keep
Keep
I/O port
Legend:
H: High
L: Low
T: High-impedance state
keep: Input pins are in the high-impedance state; output pins maintain their previous state.
DDR: Data direction register
Notes: 1. When A23E, A22E, A21E = 0 in BRCR (bus release control register).
2. When A23E, A22E, A21E = 1 in BRCR (bus release control register).
3. When CS7E, CS6E, CS5E, CS4E = 1 in CSCR (chip select control register).
4. When CS7E, CS6E, CS5E, CS4E = 0 in CSCR (chip select control register).
Rev.4.00 Aug. 20, 2007 Page 624 of 638
REJ09B0395-0400