HD6413008VF25 Datasheet, PDF (35/688 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Figure 9.23
Figure 9.24
Contention between TCOR Write and Input Capture......................................... 277
Contention between 8TCNT Byte Write and Increment in 16-Bit Count
Mode................................................................................................................... 278
Section 10 Programmable Timing Pattern Controller (TPC)
Figure 10.1 TPC Block Diagram ........................................................................................... 284
Figure 10.2 TPC Output Operation........................................................................................ 300
Figure 10.3 Timing of Transfer of Next Data Register Contents and Output (Example) ...... 301
Figure 10.4 Setup Procedure for Normal TPC Output (Example)......................................... 302
Figure 10.5 Normal TPC Output Example (Five-Phase Pulse Output) ................................. 303
Figure 10.6 Setup Procedure for Non-Overlapping TPC Output (Example) ......................... 304
Figure 10.7 Non-Overlapping TPC Output Example
(Four-Phase Complementary Non-Overlapping Pulse Output) ......................... 305
Figure 10.8 TPC Output Triggering by Input Capture (Example)......................................... 306
Figure 10.9 Non-Overlapping TPC Output............................................................................ 307
Figure 10.10 Non-Overlapping Operation and NDR Write Timing ........................................ 308
Section 11 Watchdog Timer
Figure 11.1 WDT Block Diagram ......................................................................................... 310
Figure 11.2 Format of Data Written to TCNT and TCSR ..................................................... 315
Figure 11.3 Format of Data Written to RSTCSR................................................................... 316
Figure 11.4 Operation in Watchdog Timer Mode.................................................................. 317
Figure 11.5 Interval Timer Operation.................................................................................... 318
Figure 11.6 Timing of Setting of OVF .................................................................................. 318
Figure 11.7 Timing of Setting of WRST Bit and Internal Reset............................................ 319
Figure 11.8 Contention between TCNT Write and Count up ................................................ 320
Section 12 Serial Communication Interface
Figure 12.1 SCI Block Diagram ............................................................................................ 323
Figure 12.2 Data Format in Asynchronous Communication
(Example: 8-Bit Data with Parity and 2 Stop Bits) ............................................ 353
Figure 12.3 Phase Relationship between Output Clock and Serial Data
(Asynchronous Mode) ........................................................................................ 355
Figure 12.4 Sample Flowchart for SCI Initialization............................................................. 356
Figure 12.5 Sample Flowchart for Transmitting Serial Data ................................................. 357
Figure 12.6 Example of SCI Transmit Operation in Asynchronous Mode
(8-Bit Data with Parity and One Stop Bit).......................................................... 358
Figure 12.7 Sample Flowchart for Receiving Serial Data ..................................................... 359
Figure 12.8 Example of SCI Receive Operation
(8-Bit Data with Parity and One Stop Bit).......................................................... 362
Rev.4.00 Aug. 20, 2007, Page xxxiii of xliv
REJ09B0395-0400