HD6413008VF25 Datasheet, PDF (384/688 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

12. Serial Communication Interface
The CPU can always read and write SSR, but cannot write 1 in the TDRE, RDRF, ORER, PER,
and FER flags. These flags can be cleared to 0 only if they have first been read while set to 1. The
TEND and MPB flags are read-only bits that cannot be written.
SSR is initialized to H'84 by a reset and in standby mode.
Bit 7—Transmit Data Register Empty (TDRE): Indicates that the SCI has loaded transmit data
from TDR into TSR and the next serial data can be written in TDR.
Bit 7
TDRE
0
1
Description
TDR contains valid transmit data
[Clearing condition]
Read TDRE when TDRE = 1, then write 0 in TDRE
TDR does not contain valid transmit data
[Setting conditions]
• The chip is reset or enters standby mode
(Initial value)
• The TE bit in SCR is cleared to 0
• TDR contents are loaded into TSR, so new data can be written in TDR
Bit 6—Receive Data Register Full (RDRF): Indicates that RDR contains new receive data.
Bit 6
RDRF
Description
0
RDR does not contain new receive data
[Clearing conditions]
• The chip is reset or enters standby mode
(Initial value)
• Read RDRF when RDRF = 1, then write 0 in RDRF
1
RDR contains new receive data
[Setting condition]
Serial data is received normally and transferred from RSR to RDR
Note:
The RDR contents and the RDRF flag are not affected by detection of receive errors or by
clearing of the RE bit to 0 in SCR. They retain their previous values. If the RDRF flag is still
set to 1 when reception of the next data ends, an overrun error will occur and the receive
data will be lost.
Rev.4.00 Aug. 20, 2007 Page 338 of 638
REJ09B0395-0400