HD6413008VF25 Datasheet, PDF (156/688 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

6. Bus Controller
6.2.4 Bus Release Control Register (BRCR)
BRCR is an 8-bit readable/writable register that enables address output on bus lines A₂₃ to A₂₀ and
enables or disables release of the bus to an external device.
Bit
7
6
5
4
3
2
1
0
A23E A22E A21E A20E
⎯
⎯
⎯
BRLE
Modes Initial value ¹
1
1
1
1
1
1
0
1 and 2 _{Read/Write ⎯}
⎯
⎯
⎯
⎯
⎯
⎯
R/W
Modes ^{Initial value 1}
1
1
0
1
1
1
0
3 and 4 _{Read/Write R/W}
R/W R/W
⎯
⎯
⎯
⎯
R/W
Address 23 to 20 enable
These bits enable PA₇ to PA₄ to be
used for A₂₃ to A₂₀ address output
Reserved bits
Bus release enable
Enables or disables release
of the bus to an external device
BRCR is initialized to H'FE in modes 1 and 2, and to H'EE in modes 3 and 4, by a reset and in
hardware standby mode. It is not initialized in software standby mode.
Bit 7—Address 23 Enable (A23E): Enables PA₄ to be used as the A₂₃ address output pin. Writing
0 in this bit enables A₂₃ output from PA₄. In modes other than 3 and 4, this bit cannot be modified
and PA₄ has its ordinary port functions.
Bit 7
A23E
0
1
Description
PA₄ is the A₂₃ address output pin
PA is an input/output pin
4
(Initial value)
Bit 6—Address 22 Enable (A22E): Enables PA₅ to be used as the A₂₂ address output pin. Writing
0 in this bit enables A₂₂ output from PA₅. In modes other than 3 and 4, this bit cannot be modified
and PA₅ has its ordinary port functions.
Bit 6
A22E
0
1
Description
PA is the A address output pin
5
22
PA is an input/output pin
5
(Initial value)
Rev.4.00 Aug. 20, 2007 Page 110 of 638
REJ09B0395-0400