HD6413008VF25 Datasheet, PDF (393/688 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

12. Serial Communication Interface
The BRR setting is calculated as follows:
Asynchronous mode:
φ
N=
64 × 2^2n−1 × B
× 10⁶ − 1
Synchronous mode:
φ
N=
8 × 2^2n−1 × B
× 10⁶ − 1
Legend:
B: Bit rate (bit/s)
N: BRR setting for baud rate generator (0 ≤ N ≤ 255)
φ: System clock frequency (MHz)
n: Baud rate generator input clock (n = 0, 1, 2, 3)
(For the clock sources and values of n, see the following table.)
SMR Settings
n
Clock Source
CKS1
CKS0
0
φ
0
0
1
φ/4
0
1
2
φ/16
1
0
3
φ/64
1
1
The bit rate error in asynchronous mode is calculated as follows:
φ × 10⁶
Error (%) = _{(N + 1) × B × 64 × 22n−1} − 1 × 100
Rev.4.00 Aug. 20, 2007 Page 347 of 638
REJ09B0395-0400