HD6413008VF25 Datasheet, PDF (461/688 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

14. A/D Converter
14.2 Register Descriptions
14.2.1 A/D Data Registers A to D (ADDRA to ADDRD)
Bit
ADDRn
Initial value
Read/Write
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯
000000000000 0000
RRRRRRRRRRRR RRRR
Note: n = A to D
A/D conversion data
10-bit data giving an
A/D conversion result
Reserved bits
The four A/D data registers (ADDRA to ADDRD) are 16-bit read-only registers that store the
results of A/D conversion.
An A/D conversion produces 10-bit data, which is transferred for storage into the A/D data
register corresponding to the selected channel. The upper 8 bits of the result are stored in the upper
byte of the A/D data register. The lower 2 bits are stored in the lower byte. Bits 5 to 0 of an A/D
data register are reserved bits that are always read as 0. Table 14.3 indicates the pairings of analog
input channels and A/D data registers.
The CPU can always read the A/D data registers. The upper byte can be read directly, but the
lower byte is read through a temporary register (TEMP). For details see section 14.3, CPU
Interface.
The A/D data registers are initialized to H'0000 by a reset and in standby mode.
Table 14.3 Analog Input Channels and A/D Data Registers (ADDRA to ADDRD)
Analog Input Channel
Group 0
Group 1
AN₀
AN₁
AN
2
AN
3
AN₄
AN₅
AN
6
AN
7
A/D Data Register
ADDRA
ADDRB
ADDRC
ADDRD
Rev.4.00 Aug. 20, 2007 Page 415 of 638
REJ09B0395-0400