HD6413008VF25 Datasheet, PDF (96/688 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

2. CPU
the CPU fetches a start address from the exception vector table and execution branches to that
address.
Figure 2.14 shows the stack after the exception-handling sequence.
SP−4
SP−3
SP−2
SP−1
SP (ER7)
Stack area
SP (ER7)
SP+1
SP+2
SP+3
SP+4
CCR
PC
Even
address
Before exception
handling starts
Legend:
CCR: Condition code register
SP: Stack pointer
Pushed on stack
After exception
handling ends
Notes: 1. PC is the address of the first instruction executed after the return from the
exception-handling routine.
2. Registers must be saved and restored by word access or longword access,
starting at an even address.
Figure 2.14 Stack Structure after Exception Handling
2.8.5 Bus-Released State
In this state the bus is released to a bus master other than the CPU, in response to a bus request.
The bus masters other than the CPU is an external bus master. While the bus is released, the CPU
halts except for internal operations. Interrupt requests are not accepted. For details see section 6.6,
Bus Arbiter.
2.8.6 Reset State
When the RES input goes low all current processing stops and the CPU enters the reset state. The I
bit in the condition code register is set to 1 by a reset. All interrupts are masked in the reset state.
Reset exception handling starts when the RES signal changes from low to high.
Rev.4.00 Aug. 20, 2007 Page 50 of 638
REJ09B0395-0400