HD6413008VF25 Datasheet, PDF (185/688 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

6. Bus Controller
When making a transition to software standby mode, if there is contention with a bus request from
an external bus master, the BACK and strobe states may be indefinite when the transition is made.
When using software standby mode, clear the BRLE bit to 0 in BRCR before executing the
SLEEP instruction.
6.7 Register and Pin Input Timing
6.7.1 Register Write Timing
ABWCR, ASTCR, WCRH, and WCRL Write Timing: Data written to ABWCR, ASTCR,
WCRH, and WCRL takes effect starting from the next bus cycle. Figure 6.22 shows the timing
when an instruction fetched from area 0 changes area 0 from three-state access to two-state access.
T1
T2
T3
T1
T2
T3
T1
T2
φ
Address bus
3-state access to area 0
ASTCR address
2-state access to area 0
Figure 6.22 ASTCR Write Timing
DDR and CSCR Write Timing: Data written to DDR or CSCR for the port corresponding to the
CSn pin to switch between CSn output and generic input takes effect starting from the T₃ state of
the DDR write cycle. Figure 6.23 shows the timing when the CS₁ pin is changed from generic
input
to
CS
1
output.
T1
T2
T3
φ
Address bus
P8DDR address
CS1
High-impedance
Figure 6.23 DDR Write Timing
BRCR Write Timing: Data written to BRCR to switch between A₂₃, A₂₂, A₂₁, or A₂₀ output and
generic input or output takes effect starting from the T₃ state of the BRCR write cycle. Figure 6.24
shows the timing when a pin is changed from generic input to A₂₃, A₂₂, A₂₁, or A₂₀ output.
Rev.4.00 Aug. 20, 2007 Page 139 of 638
REJ09B0395-0400