HD6413008VF25 Datasheet, PDF (344/688 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

10. Programmable Timing Pattern Controller (TPC)
10.2.10 TPC Output Mode Register (TPMR)
TPMR is an 8-bit readable/writable register that selects normal or non-overlapping TPC output for
each group.
Bit
7
6
5
4
3
2
1
0
⎯
⎯
⎯
⎯ G3NOV G2NOV G1NOV G0NOV
Initial value
1
1
1
1
0
0
0
0
Read/Write
⎯
⎯
⎯
⎯
R/W
R/W
R/W
R/W
Reserved bits
Group 3 non-overlap
Selects non-overlapping TPC
output for group 3 (TP₁₅ to TP₁₂)
Group 2 non-overlap
Selects non-overlapping TPC
output for group 2 (TP₁₁ to TP₈ )
Group 1 non-overlap
Selects non-overlapping TPC
output for group 1 (TP₇ to TP₄ )
Group 0 non-overlap
Selects non-overlapping TPC
output for group 0 (TP₃ to TP₀ )
The output trigger period of a non-overlapping TPC output waveform is set in general register B
(GRB) in the 16-bit timer channel selected for output triggering. The non-overlap margin is set in
general register A (GRA). The output values change at compare match A and B.
For details see section 10.3.4, Non-Overlapping TPC Output.
TPMR is initialized to H'F0 by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bits 7 to 4—Reserved: These bits cannot be modified and are always read as 1.
Rev.4.00 Aug. 20, 2007 Page 298 of 638
REJ09B0395-0400