HD6413008VF25 Datasheet, PDF (186/688 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

6. Bus Controller
T1
T2
T3
φ
Address bus
BRCR address
PA7 to PA4
(A23 to A20)
High-impedance
Figure 6.24 BRCR Write Timing
6.7.2 BREQ Pin Input Timing
After driving the BREQ pin low, hold it low until BACK goes low. If BREQ returns to the high
level before BACK goes lows, the bus arbiter may operate incorrectly.
To terminate the external-bus-released state, hold the BREQ signal high for at least three states. If
BREQ is high for too short an interval, the bus arbiter may operate incorrectly.
Rev.4.00 Aug. 20, 2007 Page 140 of 638
REJ09B0395-0400