HD6413008VF25 Datasheet, PDF (599/688 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Appendix B Internal I/O Registers
BCR—Bus Control Register
H'EE024
Bit
7
6
5
4
3
2
1
0
ICIS1 ICIS0
⎯
⎯
⎯
⎯
RDEA WAITE
Initial value
1
1
0*¹
0*¹
0*¹
1*²
1
0
Read/Write R/W
R/W
⎯
⎯
⎯
⎯
R/W R/W
Bus controller
Wait pin enable
0 WAIT pin wait input is disabled
1 WAIT pin wait input is enabled
Area division unit select
0 Area divisions are as follows:
Area 0: 2 Mbytes Area 4: 1.93 Mbytes
Area 1: 2 Mbytes Area 5: 4 kbytes
Area 2: 8 Mbytes Area 6: 23.75 kbytes
Area 3: 2 Mbytes Area 7: 22 bytes
1 Areas 0 to 7 are the same size
(2 Mbytes)
Idle cycle insertion 0
0 No idle cycle is inserted in case of consecutive external read and write cycles
1 Idle cycle is inserted in case of consecutive external read and write cycles
Idle cycle insertion 1
0 No idle cycle is inserted in case of consecutive external read cycles for different areas
1 Idle cycle is inserted in case of consecutive external read cycles for different areas
Notes: 1. These bits can be read and written, but must not be set to 1. Normal operation cannot be guaranteed
if 1 is written in these bits.
2. 0 must not be written in bit 2.
Rev.4.00 Aug. 20, 2007 Page 553 of 638
REJ09B0395-0400