HD6413008VF25 Datasheet, PDF (235/688 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

8. 16-Bit Timer
When bit PWM1 is set to 1 to select PWM mode, pin TIOCA₁ becomes a PWM output pin. The
output goes to 1 at compare match with GRA1, and to 0 at compare match with GRB1.
Bit 0—PWM Mode 0 (PWM0): Selects whether channel 0 operates normally or in PWM mode.
Bit 0
PWM0
0
1
Description
Channel 0 operates normally
Channel 0 operates in PWM mode
(Initial value)
When bit PWM0 is set to 1 to select PWM mode, pin TIOCA₀ becomes a PWM output pin. The
output goes to 1 at compare match with GRA0, and to 0 at compare match with GRB0.
8.2.4 Timer Interrupt Status Register A (TISRA)
TISRA is an 8-bit readable/writable register that indicates GRA compare match or input capture
and enables or disables GRA compare match and input capture interrupt requests.
Bit
Initial value
Read/Write
7
6
5
4
3
⎯ IMIEA2 IMIEA1 IMIEA0 ⎯
1
0
0
0
1
⎯ R/W R/W R/W ⎯
2
1
0
IMFA2 IMFA1 IMFA0
0
0
0
R/(W)* R/(W)* R/(W)*
Input capture/compare match
flags A2 to A0
Status flags indicating GRA
compare match or input capture
Reserved bit
Input capture/compare match interrupt enable A2 to A0
These bits enable or disable interrupts by the IMFA flags
Reserved bit
Note: * Only 0 can be written, to clear the flag.
TISRA is initialized to H'88 by a reset and in standby mode.
Bit 7—Reserved: This bit cannot be modified and is always read as 1.
Rev.4.00 Aug. 20, 2007 Page 189 of 638
REJ09B0395-0400