HD6413008VF25 Datasheet, PDF (500/688 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

17. Clock Pulse Generator
17.3 Duty Adjustment Circuit
When the oscillator frequency is 5 MHz or higher, the duty adjustment circuit adjusts the duty
cycle of the clock signal from the oscillator to generate φ.
17.4 Prescalers
The prescalers divide the system clock (φ) to generate internal clocks (φ/2 to φ/4096).
17.5 Frequency Divider
The frequency divider divides the duty-adjusted clock signal to generate the system clock (φ). The
frequency division ratio can be changed dynamically by modifying the value in DIVCR, as
described below. Power consumption in the chip is reduced in almost direct proportion to the
frequency division ratio. The system clock generated by the frequency divider can be output at the
φ pin.
17.5.1 Register Configuration
Table 17.4 summarizes the frequency division register.
Table 17.4 Frequency Division Register
Address*
Name
Abbreviation
R/W
H'EE01B
Division control register
DIVCR
R/W
Note: * Lower 20 bits of the address in advanced mode.
Initial Value
H'FC
Rev.4.00 Aug. 20, 2007 Page 454 of 638
REJ09B0395-0400