HD6413008VF25 Datasheet, PDF (373/688 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

12.2.3 Transmit Shift Register (TSR)
TSR is the register that transmits serial data.
Bit
7
6
5
4
12. Serial Communication Interface
3
2
1
0
Read/Write
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
The SCI loads transmit data from TDR to TSR, then transmits the data serially from the TxD pin,
LSB (bit 0) first. After transmitting one data byte, the SCI automatically loads the next transmit
data from TDR into TSR and starts transmitting it. If the TDRE flag is set to 1 in SSR, however,
the SCI does not load the TDR contents into TSR. The CPU cannot read or write RSR directly.
12.2.4 Transmit Data Register (TDR)
TDR is an 8-bit register that stores data for serial transmission.
Bit
7
6
5
4
3
2
1
0
Initial value
1
1
Read/Write
R/W
R/W
1
1
1
1
R/W
R/W
R/W
R/W
1
1
R/W
R/W
When the SCI detects that TSR is empty, it moves transmit data written in TDR from TDR into
TSR and starts serial transmission. Continuous serial transmission is possible by writing the next
transmit data in TDR during serial transmission from TSR.
The CPU can always read and write TDR. TDR is initialized to H'FF by a reset and in standby
mode.
Rev.4.00 Aug. 20, 2007 Page 327 of 638
REJ09B0395-0400