HD6413008VF25 Datasheet, PDF (442/688 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

13. Smart Card Interface
13.3.5 Clock
Only an internal clock generated by the on-chip baud rate generator can be used as the
transmit/receive clock for the smart card interface. The bit rate is set with the bit rate register
(BRR) and the CKS1 and CKS0 bits in the serial mode register (SMR). The equation for
calculating the bit rate is shown below. Table 13.5 shows some sample bit rates.
If clock output is selected with CKE0 set to 1, a clock with a frequency of 372 times the bit rate is
output from the SCK pin.
φ
B = _{1488 × 22n−1 × (N + 1)} × 10⁶
where, N: BRR setting (0 ≤ N ≤ 255)
B: Bit rate (bit/s)
φ: Operating frequency (MHz)
n: See table 13.4
Table 13.4 n-Values of CKS1 and CKS0 Settings
n
CKS1
CKS0
0
0
0
1
1
2
1
0
3
1
Note: If the gear function is used to divide the clock frequency, use the divided frequency to
calculate the bit rate. The equation above applies directly to 1/1 frequency division.
Table 13.5 Bit Rates (bits/s) for Various BRR Settings (When n = 0)
φ (MHz)
N 7.1424 10.00 10.7136 13.00 14.2848 16.00 18.00 20.00 25.00
0 9600.0 13440.9 14400.0 17473.1 19200.0 21505.4 24193.5 26881.7 33602.2
1 4800.0 6720.4 7200.0 8736.6 9600.0 10752.7 12096.8 13440.9 16801.1
2 3200.0 4480.3 4800.0 5824.4 6400.0 7168.5 8064.5 8960.6 11200.7
Note: Bit rates are rounded off to two decimal places.
Rev.4.00 Aug. 20, 2007 Page 396 of 638
REJ09B0395-0400