|
HD6413008VF25 Datasheet, PDF (529/688 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents | |||
|
◁ |
19. Electrical Characteristics
Table 19.7 Timing of On-Chip Supporting Modules
Condition: Ta = â20°C to +75°C (regular specifications), Ta = â40°C to +85°C (wide-range
specifications)
Condition A: VCC = 3.0 to 3.6 V, AVCC = 3.0 to 3.6 V, VREF = 3.0 to AVCC, VSS = AVSS = 0 V,
fmax = 25 MHz
Condition B: VCC = 5.0 V ±10%, AVCC = 5.0 V ±10%, VREF = 4.5 to AVCC, VSS = AVSS = 0 V,
fmax = 20 MHz
Condition C: VCC = 5.0 V ±10%, AVCC = 5.0 V ±10%, VREF = 4.5 to AVCC, VSS = AVSS = 0 V,
fmax = 25 MHz
Module Item
Ports
and
TPC
Output data delay time
Input data setup time
Input data hold time
16-bit Timer output delay time
timer Timer input setup time
Timer clock input setup time
Timer clock
pulse width
Single edge
Both edges
8-bit
timer
Timer output delay time
Timer input setup time
Timer clock input setup time
Timer clock
pulse width
Single edge
Both edges
Condition
A
B and C
Symbol Min Max Min Max Unit
tPWD
⯠50
t
50 â¯
PRS
t
50 â¯
PRH
t
⯠50
TOCD
tTICS
50 â¯
tTCKS
50 â¯
t
1.5 â¯
TCKWH
t
TCKWL
2.5 â¯
t
⯠50
TOCD
tTICS
50 â¯
tTCKS
50 â¯
tTCKWH
1.5
â¯
t
TCKWL
2.5 â¯
⯠50 ns
50 ⯠ns
50 ⯠ns
⯠50 ns
50 ⯠ns
50 ⯠ns
1.5 ⯠t
cyc
2.5 ⯠t
cyc
⯠50 ns
50 ⯠ns
50 ⯠ns
1.5 ⯠tcyc
2.5 ⯠t
cyc
Test
Conditions
Figure 19.11
Figure 19.12
Figure 19.13
Figure 19.12
Figure 19.13
Rev.4.00 Aug. 20, 2007 Page 483 of 638
REJ09B0395-0400
|
▷ |