HD6413008VF25 Datasheet, PDF (121/688 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

5. Interrupt Controller
Section 5 Interrupt Controller
5.1 Overview
5.1.1 Features
The interrupt controller has the following features:
• Interrupt priority registers (IPRs) for setting interrupt priorities
Interrupts other than NMI can be assigned to two priority levels on a module-by-module basis
in interrupt priority registers A and B (IPRA and IPRB).
• Three-level enabling/disabling by the I and UI bits in the CPU's condition code register (CCR)
and the UE bit in the system control register (SYSCR)
• Seven external interrupt pins
NMI has the highest priority and is always accepted; either the rising or falling edge can be
selected. For each of IRQ₅ to IRQ₀, sensing of the falling edge or level sensing can be selected
independently.
Rev.4.00 Aug. 20, 2007 Page 75 of 638
REJ09B0395-0400