HD6413008VF25 Datasheet, PDF (170/688 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

6. Bus Controller
Table 6.4 Data Buses Used and Valid Strobes
Area
8-bit access
area
Access Read/
Size
Write
Byte
Read
Write
Valid
Address Strobe
⎯
RD
⎯
HWR
Upper Data Bus
(D to D )
15
8
Valid
Lower Data Bus
(D to D )
7
0
Invalid
Undetermined data
16-bit access Byte
Read Even
RD
area
Odd
Valid
Invalid
Invalid
Valid
Write Even
HWR Valid
Undetermined data
Odd
LWR Undetermined data Valid
Word Read ⎯
RD
Valid
Valid
Write ⎯
HWR, Valid
LWR
Valid
Notes: 1. Undetermined data means that unpredictable data is output.
2. Invalid means that the bus is in the input state and the input is ignored.
6.4.4 Memory Areas
The initial state of each area is basic bus interface, three-state access space. The initial bus width is
selected according to the operating mode.
Areas 0 to 6: In the H8/3008, the entire space of areas 0 to 6 is external space.
When area 0 to 6 external space is accessed, the CS₀ to CS₆ pin signals respectively can be output.
The size of areas 0 to 6 is 128 kbytes in modes 1 and 2, and 2 Mbytes in modes 3 and 4.
Area 7: Area 7 includes the on-chip RAM and internal I/O registers. In the H8/3008, the space
excluding the on-chip RAM and I/O registers is external space. The on-chip RAM is enabled when
the RAME bit in the system control register (SYSCR) is set to 1; when the RAME bit is cleared to
0, the on-chip RAM is disabled and the corresponding space becomes external space .
When area 7 external space is accessed, the CS₇ signal can be output.
The size of area 7 is 128 kbytes in modes 1 and 2, and 2 Mbytes in modes 3 and 4.
Rev.4.00 Aug. 20, 2007 Page 124 of 638
REJ09B0395-0400