HD6413008VF25 Datasheet, PDF (426/688 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

12. Serial Communication Interface
The receive margin in asynchronous mode can therefore be expressed as shown in equation (1).
M = (0.5 − ¹ ) − (L − 0.5) F − ^{D − 0.5} (1 + F) × 100% . . . . . . . . (1)
2N
N
Legend:
M: Receive margin (%)
N: Ratio of clock frequency to bit rate (N = 16)
D: Clock duty cycle (D = 0 to 1.0)
L: Frame length (L = 9 to 12)
F: Absolute deviation of clock frequency
From equation (1), if F = 0 and D = 0.5, the receive margin is 46.875%, as given by equation (2).
When D = 0.5 and F = 0:
M = (0.5 − ¹ ) × 100%
2 × 16
= 46.875%
. . . . . . . . (2)
This is a theoretical value. A reasonable margin to allow in system designs is 20% to 30%.
Restrictions on Use of an External Clock Source:
• When an external clock source is used for the serial clock, after updates TDR, allow an
inversion of at least five system clock (φ) cycles before input of the serial clock to start
transmitting. If the serial clock is input within four states of the TDR update, a malfunction
may occur. (See figure 12.22)
SCK
t
TDRE
D0
D1
D2
D3
D4
D5
D6
D7
Note: In operation with an external clock source, be sure that t >4 states.
Figure 12.22 Example of Synchronous Transmission
Rev.4.00 Aug. 20, 2007 Page 380 of 638
REJ09B0395-0400