HD6413008VF25 Datasheet, PDF (157/688 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

6. Bus Controller
Bit 5—Address 21 Enable (A21E): Enables PA₆ to be used as the A₂₁ address output pin. Writing
0 in this bit enables A₂₁ output from PA₆. In modes other than 3 and 4, this bit cannot be modified
and PA₆ has its ordinary port functions.
Bit 5
A21E
0
1
Description
PA is the A address output pin
6
21
PA is an input/output pin
6
(Initial value)
Bit 4—Address 20 Enable (A20E): Enables PA₇ to be used as an address output pin. When 0 is
written to this bit, PA₇ functions as address output A₂₀. In modes 3 and 4, PA₇ functions as an
address output pin, and in modes 1 and 2, as a normal port pin.
Bit 4
A20E
0
1
Description
PA₇ is the A₂₀ address output pin (In mode 3 or 4)
PA₇ is an input/output pin (In mode 1 or 2)
Bits 3 to 1—Reserved: These bits cannot be modified and are always read as 1.
Bit 0—Bus Release Enable (BRLE): Enables or disables release of the bus to an external device.
Bit 0
BRLE
0
1
Description
The bus cannot be released to an external device
BREQ and BACK can be used as input/output pins
The bus can be released to an external device
(Initial value)
6.2.5 Bus Control Register (BCR)
Bit
7
6
5
4
3
2
1
0
ICIS1
ICIS0
⎯
⎯
—
⎯
RDEA WAITE
Initial value
1
1
0*¹
0*¹
0*¹
1*²
1
0
Read/Write R/W
R/W
⎯
⎯
⎯
⎯
R/W
R/W
Notes: 1. 1 must not be written in bits 5 to 3.
2. 0 must not be written in bit 2.
Rev.4.00 Aug. 20, 2007 Page 111 of 638
REJ09B0395-0400