HD6413008VF25 Datasheet, PDF (38/688 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Figure 19.9
Figure 19.10
Figure 19.11
Figure 19.12
Figure 19.13
Figure 19.14
Figure 19.15
Basic Bus Cycle: Three-State Access with One Wait State ............................... 494
Bus-Release Mode Timing ................................................................................. 494
TPC and I/O Port Input/Output Timing.............................................................. 495
Timer Input/Output Timing................................................................................ 495
Timer External Clock Input Timing ................................................................... 496
SCI Input Clock Timing ..................................................................................... 496
SCI Input/Output Timing in Synchronous Mode ............................................... 496
Appendix C I/O Port Block Diagrams
Figure C.1 Port 4 Block Diagram......................................................................................... 598
Figure C.2 (a) Port 6 Block Diagram (Pin P6₀).......................................................................... 599
Figure C.2 (b) Port 6 Block Diagram (Pin P6₁).......................................................................... 600
Figure C.2 (c) Port 6 Block Diagram (Pin P6₂).......................................................................... 601
Figure C.2 (d) Port 6 Block Diagram (Pin P6₇).......................................................................... 602
Figure C.3 (a) Port 7 Block Diagram (Pins P7₀ to P7₅).............................................................. 603
Figure C.3 (b) Port 7 Block Diagram (Pins P7₆ and P7₇) ........................................................... 603
Figure C.4 (a) Port 8 Block Diagram (Pin P8₀).......................................................................... 604
Figure C.4 (b) Port 8 Block Diagram (Pins P8₁ and P8₂) ........................................................... 605
Figure C.4 (c) Port 8 Block Diagram (Pin P8₃).......................................................................... 606
Figure C.4 (d) Port 8 Block Diagram (Pin P8₄).......................................................................... 607
Figure C.5 (a) Port 9 Block Diagram (Pin P9₀).......................................................................... 608
Figure C.5 (b) Port 9 Block Diagram (Pin P9₁).......................................................................... 609
Figure C.5 (c) Port 9 Block Diagram (Pin P9₂).......................................................................... 610
Figure C.5 (d) Port 9 Block Diagram (Pin P9₃).......................................................................... 611
Figure C.5 (e) Port 9 Block Diagram (Pin P9₄).......................................................................... 612
Figure C.5 (f) Port 9 Block Diagram (Pin P9₅).......................................................................... 613
Figure C.6 (a) Port A Block Diagram (Pins PA₀ and PA₁)......................................................... 614
Figure C.6 (b) Port A Block Diagram (Pins PA₂ and PA₃)......................................................... 615
Figure C.6 (c) Port A Block Diagram (Pins PA₄ to PA₇) ........................................................... 616
Figure C.7 (a) Port B Block Diagram (Pins PB₀ and PB₂) ......................................................... 617
Figure C.7 (b)
Port
B Block
Diagram
(Pins
PB
1
and
PB₃) .........................................................
618
Figure C.7 (c) Port B Block Diagram (Pin PB₄) ........................................................................ 619
Figure C.7 (d) Port B Block Diagram (Pin PB₅) ........................................................................ 620
Figure C.7 (e) Port B Block Diagram (Pin PB₆) ........................................................................ 621
Figure C.7 (f) Port B Block Diagram (Pin PB₇) ........................................................................ 622
Appendix D Pin States
Figure D.1 Reset during Memory Access (Modes 1 and 2).................................................. 626
Figure D.2 Reset during Memory Access (Modes 3 and 4).................................................. 627
Rev.4.00 Aug. 20, 2007 Page xxxvi of xliv
REJ09B0395-0400