HD6413008VF25 Datasheet, PDF (78/688 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

2. CPU
Instruction Size* Function
DIVXU
B/W Rd ÷ Rs → Rd
Performs unsigned division on data in two general registers: either 16 bits ÷ 8
bits → 8-bit quotient and 8-bit remainder or 32 bits ÷ 16 bits → 16-bit quotient
and 16-bit remainder
DIVXS
B/W Rd ÷ Rs → Rd
Performs signed division on data in two general registers: either 16 bits ÷ 8
bits → 8-bit quotient and 8-bit remainder, or 32 bits ÷ 16 bits → 16-bit
quotient and 16-bit remainder
CMP
B/W/L Rd − Rs, Rd − #IMM
Compares data in a general register with data in another general register or
with immediate data, and sets CCR according to the result.
NEG
B/W/L 0 − Rd → Rd
Takes the two's complement (arithmetic complement) of data in a general
register.
EXTS
W/L Rd (sign extension) → Rd
Extends byte data in the lower 8 bits of a 16-bit register to word data, or
extends word data in the lower 16 bits of a 32-bit register to longword data,
by extending the sign bit.
EXTU
W/L Rd (zero extension) → Rd
Extends byte data in the lower 8 bits of a 16-bit register to word data, or
extends word data in the lower 16 bits of a 32-bit register to longword data,
by padding with zeros.
Note: * Size refers to the operand size.
B: Byte
W: Word
L: Longword
Rev.4.00 Aug. 20, 2007 Page 32 of 638
REJ09B0395-0400