HD6413008VF25 Datasheet, PDF (282/688 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

8. 16-Bit Timer
Contention between Counter Clearing by Input Capture and Counter Increment: If an input
capture signal and counter increment signal occur simultaneously, the counter is cleared according
to the input capture signal. The counter is not incremented by the increment signal. The value
before the counter is cleared is transferred to the general register. See figure 8.43.
φ
Input capture signal
Counter clear signal
16TCNT input clock
16TCNT
N
H'0000
GR
N
Figure 8.43 Contention between Counter Clearing by Input Capture and Counter
Increment
Rev.4.00 Aug. 20, 2007 Page 236 of 638
REJ09B0395-0400