HD6413008VF25 Datasheet, PDF (37/688 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Figure 14.4
Figure 14.5
Figure 14.6
Figure 14.7
Figure 14.8
Figure 14.9
Figure 14.10
Figure 14.11
Example of A/D Converter Operation
(Scan Mode, Channels AN₀ to AN₂ Selected) .................................................... 424
A/D Conversion Timing ..................................................................................... 426
External Trigger Input Timing ........................................................................... 427
Example of Analog Input Protection Circuit ...................................................... 429
Analog Input Pin Equivalent Circuit .................................................................. 429
A/D Converter Accuracy Definitions (1) ........................................................... 431
A/D Converter Accuracy Definitions (2) ........................................................... 432
Analog Input Circuit (Example) ......................................................................... 433
Section 15 D/A Converter
Figure 15.1 D/A Converter Block Diagram........................................................................... 436
Figure 15.2 Example of D/A Converter Operation................................................................ 441
Section 16 RAM
Figure 16.1 RAM Block Diagram ......................................................................................... 444
Section 17 Clock Pulse Generator
Figure 17.1 Block Diagram of Clock Pulse Generator .......................................................... 448
Figure 17.2 Connection of Crystal Resonator (Example) ...................................................... 449
Figure 17.3 Crystal Resonator Equivalent Circuit ................................................................. 450
Figure 17.4 Oscillator Circuit Block Board Design Precautions ........................................... 451
Figure 17.5 External Clock Input (Examples) ....................................................................... 451
Figure 17.6 External Clock Input Timing.............................................................................. 453
Figure 17.7 External Clock Output Settling Delay Timing ................................................... 453
Section 18 Power-Down State
Figure 18.1 NMI Timing for Software Standby Mode (Example) ........................................ 467
Figure 18.2 Hardware Standby Mode Timing ....................................................................... 469
Figure 18.3 Starting and Stopping of System Clock Output.................................................. 470
Section 19 Electrical Characteristics
Figure 19.1 Darlington Pair Drive Circuit (Example) ........................................................... 478
Figure 19.2 Output Load Circuit............................................................................................ 484
Figure 19.3 Oscillator Settling Timing .................................................................................. 488
Figure 19.4 Reset Input Timing ............................................................................................. 489
Figure 19.5 Reset Output Timing .......................................................................................... 489
Figure 19.6 Interrupt Input Timing........................................................................................ 490
Figure 19.7 Basic Bus Cycle: Two-State Access................................................................... 492
Figure 19.8 Basic Bus Cycle: Three-State Access................................................................. 493
Rev.4.00 Aug. 20, 2007, Page xxxv of xliv
REJ09B0395-0400