HD6413008VF25 Datasheet, PDF (361/688 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

11. Watchdog Timer
Bit 6—Reset Output Enable (RSTOE): Enables or disables external output at the RESO pin of
the reset signal generated if TCNT overflows during watchdog timer operation. Note that there is
no RESO pin in the versions with on-chip flash memory.
Bit 6
RSTOE Description
0
Reset signal is not output externally
1
Reset signal is output externally
(Initial value)
Bits 5 to 0—Reserved: These bits cannot be modified and are always read as 1.
11.2.4 Notes on Register Access
The watchdog timer's TCNT, TCSR, and RSTCSR registers differ from other registers in being
more difficult to write. The procedures for writing and reading these registers are given below.
Writing to TCNT and TCSR: These registers must be written by a word transfer instruction.
They cannot be written by byte instructions. Figure 11.2 shows the format of data written to
TCNT and TCSR. TCNT and TCSR both have the same write address. The write data must be
contained in the lower byte of the written word. The upper byte must contain H'5A (password for
TCNT) or H'A5 (password for TCSR). This transfers the write data from the lower byte to TCNT
or TCSR.
TCNT write
15
Address H'FFF8C *
H'5A
87
0
Write data
TCSR write
15
Address H'FFF8C *
H'A5
87
0
Write data
Note: * Lower 20 bits of the address in advanced mode.
Figure 11.2 Format of Data Written to TCNT and TCSR
Rev.4.00 Aug. 20, 2007 Page 315 of 638
REJ09B0395-0400