HD6413008VF25 Datasheet, PDF (620/688 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Appendix B Internal I/O Registers
8TCR2—Timer Control Register 2
8TCR3—Timer Control Register 3
H'FFF90
H'FFF91
8-bit timer channel 2
8-bit timer channel 3
Bit
7
6
CMIEB CMIEA
Initial value
0
0
Read/Write R/W
R/W
5
4
3
2
OVIE CCLR1 CCLR0 CKS2
0
0
0
0
R/W
R/W
R/W
R/W
1
CKS1
0
R/W
0
CKS0
0
R/W
Clock select 2 to 0
CSK2 CSK1 CSK0
Description
0 Clock input is disabled
0
1
Internal clock: counted on rising edge
of φ/8
Internal clock: counted on rising edge
0
1
0 _{of φ/64}
1
Internal clock: counted on rising edge
of φ/8192
Channel 2:
0
0
Count on 8TCNT3 overflow signal*
Channel 3:
Count on 8TCNT2 compare match A*
1
1 External clock: counted on falling edge
0 External clock: counted on rising edge
1
1 ^{External clock: counted on both}
rising and falling edges
Note: * If the clock input of channel 2 is the 8TCNT3 overflow
signal and that of channel 3 is the 8TCNT2 compare
match signal, no incrementing clock is generated. Do
not use this setting.
Counter clear 1 and 0
0 Clearing is disabled
0
1 Cleared by compare match A
0 Cleared by compare match B/input capture B
1
1 Cleared by input capture B
Timer overflow interrupt enable
0 OVI interrupt requested by OVF is disabled
1 OVI interrupt requested by OVF is enabled
Compare match interrupt enable A
0 CMIA interrupt requested by CMFA is disabled
1 CMIA interrupt requested by CMFA is enabled
Compare match interrupt enable B
0 CMIB interrupt requested by CMFB is disabled
1 CMIB interrupt requested by CMFB is enabled
Rev.4.00 Aug. 20, 2007 Page 574 of 638
REJ09B0395-0400