HD6413008VF25 Datasheet, PDF (246/688 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

8. 16-Bit Timer
Bits 6 and 5—Counter Clear 1 and 0 (CCLR1, CCLR0): These bits select how 16TCNT is
cleared.
Bit 6
Bit 5
CCLR1 CCLR0 Description
0
0
16TCNT is not cleared
(Initial value)
1
16TCNT is cleared by GRA compare match or input capture*¹
1
0
16TCNT is cleared by GRB compare match or input capture*¹
1
Synchronous clear: 16TCNT is cleared in synchronization with other
synchronized timers*²
Notes: 1. 16TCNT is cleared by compare match when the general register functions as an output
compare register, and by input capture when the general register functions as an input
capture register.
2. Selected in TSNC.
Bits 4 and 3—Clock Edge 1 and 0 (CKEG1, CKEG0): These bits select external clock input
edges when an external clock source is used.
Bit 4
CKEG1
0
1
Bit 3
CKEG0
0
1
⎯
Description
Count rising edges
Count falling edges
Count both edges
(Initial value)
When channel 2 is set to phase counting mode, bits CKEG1 and CKEG0 in 16TCR2 are ignored.
Phase counting takes precedence.
Rev.4.00 Aug. 20, 2007 Page 200 of 638
REJ09B0395-0400