HD6413008VF25 Datasheet, PDF (608/688 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Appendix B Internal I/O Registers
16TCR0—Timer Control Register 0
H'FFF68
16-bit timer channel 0
Bit
7
6
5
4
3
2
1
0
⎯ CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0
Initial value
1
Read/Write ⎯
0
0
0
0
0
0
0
R/W
R/W R/W
R/W
R/W
R/W R/W
Timer prescaler 2 to 0
Bit 2
Bit 1
Bit 0
TPSC2
0
TPSC1
0
1
TPSC0
0
1
0
1
0
0
1
1
0
1
1
Description
Internal clock : φ
Internal clock : φ / 2
Internal clock : φ / 4
Internal clock : φ / 8
External clock A : TCLKA input
External clock B : TCLKB input
External clock C : TCLKC input
External clock D : TCLKD input
(Initial value)
Clock edge 1 and 0
Bit 4
Bit 3
CKEG
0
0
1
CKEG0
0
1
⎯
Rising edges counted
Falling edges counted
Both edges counted
Description
(Initial value)
Counter clear 1 and 0
Bit 6
CCLR1
Bit 5
CCLR0
Description
0
0
16TCNT is not cleared
(Initial value)
1
16TCNT is cleared by GRA compare match or input capture
1
0
16TCNT is cleared by GRB compare match or input capture
Synchronous clear : 16TCNT is cleared in synchronization with
1
other synchronized timers
Rev.4.00 Aug. 20, 2007 Page 562 of 638
REJ09B0395-0400