HD6413008VF25 Datasheet, PDF (435/688 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

13. Smart Card Interface
Bits 3 to 0: These bits operate as in normal serial communication. For details see section 12.2.7,
Serial Status Register (SSR). The setting conditions for transmit end (TEND), however, are
modified as follows.
Bit 2
TEND
Description
0
Transmission is in progress
[Clearing condition]
Software reads TDRE while it is set to 1, then writes 0 in the TDRE flag.
1
End of transmission
[Setting conditions]
(Initial value)
• The chip is reset or enters standby mode.
• The TE bit and FER/ERS bit are both cleared to 0 in SCR.
• TDRE is 1 and FER/ERS is 0 at a time 2.5 etu after the last bit of a 1-byte serial
character is transmitted (normal transmission).
Note: An etu (elementary time unit) is the time needed to transmit one bit.
13.2.3 Serial Mode Register (SMR)
The function of SMR bit 7 is modified in smart card interface mode. This change also causes a
modification to the function of bits 1 and 0 in the serial control register (SCR).
Bit
7
6
5
4
3
2
1
0
GM
CHR
PE
O/E STOP MP CKS1 CKS0
Initial value
0
0
0
0
0
0
0
0
Read/Write R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit 7—GSM Mode (GM): With the normal smart card interface, this bit is cleared to 0. Setting
this bit to 1 selects GSM mode, an additional mode for controlling the timing for setting the
TEND flag that indicates completion of transmission, and the type of clock output used. The
details of the additional clock output control mode are specified by the CKE1 and CKE0 bits in
the serial control register (SCR).
Rev.4.00 Aug. 20, 2007 Page 389 of 638
REJ09B0395-0400