HD6413008VF25 Datasheet, PDF (116/688 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

4. Exception Handling
φ
Vector fetch
Internal
processing
Prefetch of first
program instruction
RES
Address bus
(1)
(3)
(5)
RD
HWR, LWR
High
D₁₅ to D₀
(2)
(4)
(6)
(1), (3)
(2), (4)
(5)
(6)
Address of reset exception handling vector: (1) = H'000000, (3) = H'000002
Start address (contents of reset exception handling vector address)
Start address
First instruction of program
Note: After a reset, the wait-state controller inserts three wait states in every bus cycle.
Figure 4.3 Reset Sequence (Modes 2 and 4)
4.2.3 Interrupts after Reset
If an interrupt is accepted after a reset but before the stack pointer (SP) is initialized, PC and CCR
will not be saved correctly, leading to a program crash. To prevent this, all interrupt requests,
including NMI, are disabled immediately after a reset exception handling. The first instruction of
the program is always executed immediately after the reset state ends. This instruction should
initialize the stack pointer (example: MOV.L #xx:32, SP).
Rev.4.00 Aug. 20, 2007 Page 70 of 638
REJ09B0395-0400