HD6413008VF25 Datasheet, PDF (84/688 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

2. CPU
Table 2.10 Block Transfer Instruction
Instruction Size Function
EEPMOV.B ⎯
if R4L ≠ 0 then
repeat @ER5+ → @ER6+, R4L − 1 → R4L
until R4L = 0
else next;
EEPMOV.W ⎯
if R4 ≠ 0 then
repeat @ER5+ → @ER6+, R4 − 1 → R4
until R4 = 0
else next;
Block transfer instruction. This instruction transfers the number of data bytes
specified by R4L or R4, starting from the address indicated by ER5, to the
location starting at the address indicated by ER6. At the end of the transfer,
the next instruction is executed.
2.6.4 Basic Instruction Formats
The H8/300H instructions consist of 2-byte (word) units. An instruction consists of an operation
field (OP field), a register field (r field), an effective address extension (EA field), and a condition
field (cc).
Operation Field: Indicates the function of the instruction, the addressing mode, and the operation
to be carried out on the operand. The operation field always includes the first 4 bits of the
instruction. Some instructions have two operation fields.
Register Field: Specifies a general register. Address registers are specified by 3 bits, data registers
by 3 bits or 4 bits. Some instructions have two register fields. Some have no register field.
Effective Address Extension: Eight, 16, or 32 bits specifying immediate data, an absolute
address, or a displacement. A 24-bit address or displacement is treated as 32-bit data in which the
first 8 bits are 0 (H'00).
Condition Field: Specifies the branching condition of Bcc instructions.
Figure 2.9 shows examples of instruction formats.
Rev.4.00 Aug. 20, 2007 Page 38 of 638
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