HD6413008VF25 Datasheet, PDF (321/688 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

9. 8-Bit Timers
9.7.4 Contention between TCOR Read and Input Capture
If an input capture signal occurs in the T₃ state of a TCOR read cycle, the value before input
capture is read. Figure 9.21 shows the timing in this case.
TCORB read cycle
T1
T2
T3
φ
Address bus
TCORB address
Internal read signal
Input capture signal
TCORB
N
M
Internal data bus
N
Figure 9.21 Contention between TCOR Read and Input Capture
Rev.4.00 Aug. 20, 2007 Page 275 of 638
REJ09B0395-0400