HD6413008VF25 Datasheet, PDF (464/688 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

14. A/D Converter
Bits 2 to 0—Channel Select 2 to 0 (CH2 to CH0): These bits and the SCAN bit select the analog
input channels. Clear the ADST bit to 0 before changing the channel selection.
Group
Selection
CH2
0
1
Channel Selection
CH1
CH0
0
0
1
1
0
1
0
0
1
1
0
1
Description
Single Mode
Scan Mode
AN₀ (Initial value)
AN₁
AN
2
AN
3
AN₄
AN₅
AN₆
AN
7
AN₀
AN₀, AN₁
AN to AN
0
2
AN to AN
0
3
AN₄
AN₄, AN₅
AN₄ to AN₆
AN to AN
4
7
14.2.3 A/D Control Register (ADCR)
Bit
7
6
5
4
3
2
1
0
TRGE
⎯
⎯
⎯
⎯
⎯
⎯
⎯
Initial value
0
1
1
1
1
1
1
0
Read/Write
R/W
⎯
⎯
⎯
⎯
⎯
⎯
R/W
Reserved bits
Trigger enable
Enables or disables starting of A/D conversion
by an external trigger or 8-bit timer compare match
ADCR is an 8-bit readable/writable register that enables or disables starting of A/D conversion by
external trigger input or an 8-bit timer compare match signal. ADCR is initialized to H'7F by a
reset and in standby mode.
Rev.4.00 Aug. 20, 2007 Page 418 of 638
REJ09B0395-0400