HD6413008VF25 Datasheet, PDF (98/688 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

2. CPU
Bus cycle
T₁ state
T₂ state
φ
Internal address bus
Address
Internal read signal
Internal data bus
(read access)
Read data
Internal write signal
Internal data bus
(write access)
Write data
Figure 2.15 On-Chip Memory Access Cycle
φ
Address bus
T₁
T₂
Address
AS, RD, HWR, LWR
D₁₅ to D₀
High
High impedance
Figure 2.16 Pin States during On-Chip Memory Access (Address Update Mode 1)
2.9.3 On-Chip Supporting Module Access Timing
The on-chip supporting modules are accessed in three states. The data bus is 8 or 16 bits wide,
depending on the internal I/O register being accessed. Figure 2.17 shows the on-chip supporting
module access timing. Figure 2.18 indicates the pin states.
Rev.4.00 Aug. 20, 2007 Page 52 of 638
REJ09B0395-0400