HD6413008VF25 Datasheet, PDF (516/688 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

18. Power-Down State
function and becomes a port pin. If its port DDR bit is set to 1, the pin becomes a data output pin,
and its output may collide with external SCI transmit data. Data collision should be prevented by
clearing the port DDR bit to 0 or taking other appropriate action.
Register Resetting: When an on-chip supporting module is halted by the module standby
function, all its registers are initialized. To restart the module, after its MSTCR bit is cleared to 0,
its registers must be set up again. It is not possible to write to the registers while the MSTCR bit is
set to 1.
18.7 System Clock Output Disabling Function
Output of the system clock (φ) can be controlled by the PSTOP bit in MSTCRH. When the
PSTOP bit is set to 1, output of the system clock halts and the φ pin is placed in the high-
impedance state. Figure 18.3 shows the timing of the stopping and starting of system clock output.
When the PSTOP bit is cleared to 0, output of the system clock is enabled. Table 18.4 indicates
the state of the φ pin in various operating states.
φ pin
MSTCRH write cycle
(PSTOP = 1)
T1 T2 T3
High impedance
MSTCRH write cycle
(PSTOP = 0)
T1 T2 T3
Figure 18.3 Starting and Stopping of System Clock Output
Table 18.4 φ Pin State in Various Operating States
Operating State
Hardware standby
Software standby
Sleep mode
Normal operation
PSTOP = 0
High impedance
Always high
System clock output
System clock output
PSTOP = 1
High impedance
High impedance
High impedance
High impedance
Rev.4.00 Aug. 20, 2007 Page 470 of 638
REJ09B0395-0400