HD6413008VF25 Datasheet, PDF (225/688 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

8. 16-Bit Timer
8.1.2 Block Diagrams
16-bit timer Block Diagram (Overall): Figure 8.1 is a block diagram of the 16-bit timer.
TCLKA to TCLKD
φ, φ/2, φ/4, φ/8
TIOCA₀ to TIOCA₂
TIOCB₀ to TIOCB₂
Clock selector
Control logic
Module data bus
IMIA0 to IMIA2
IMIB0 to IMIB2
OVI0 to OVI2
TSTR
TSNR
TMDR
TOLR
TISRA
TISRB
TISRC
Legend:
TSTR: Timer start register (8 bits)
TSNR: Timer synchro register (8 bits)
TMDR: Timer mode register (8 bits)
TOLR: Timer output level setting register (8 bits)
TISRA: Timer interrupt status register A (8 bits)
TISRB: Timer interrupt status register B (8 bits)
TISRC: Timer interrupt status register C (8 bits)
Figure 8.1 16-bit timer Block Diagram (Overall)
Rev.4.00 Aug. 20, 2007 Page 179 of 638
REJ09B0395-0400