HD6413008VF25 Datasheet, PDF (603/688 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

TMDR—Timer Mode Register
Bit 7
6
5
4
⎯ MDF FDIR ⎯
Initial value 1
0
0
1
Read/Write ⎯
R/W R/W
⎯
Appendix B Internal I/O Registers
H'FFF62 16-bit timer (all channels)
3
2
1
0
⎯ PWM2 PWM1 PWM0
1
0
0
0
⎯
R/W R/W R/W
PWM mode 0
0 Channel 0 operates normally (Initial value)
1 Channel 0 operates in PWM mode
PWM mode 1
0 Channel 1 operates normally (Initial value)
1 Channel 1 operates in PWM mode
PWM mode 2
0 Channel 2 operates normally (Initial value)
1 Channel 2 operates in PWM mode
Flag direction
0 ^{OVF is set to 1 in TISRC when 16TCNT2}
overflows or underflows
(Initial value)
OVF is set to 1 in TISRC when 16TCNT2
1 _overflows
Phase counting mode
0 Channel 2 operates normally
(Initial value)
1 Channel 2 operates in phase counting mode
Rev.4.00 Aug. 20, 2007 Page 557 of 638
REJ09B0395-0400