HD6413008VF25 Datasheet, PDF (86/688 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

2. CPU
Before Execution of BCLR Instruction
Input/output
DDR
P4₇
Input
0
P4₆
Input
0
P4₅
Output
1
P4₄
Output
1
P4₃
Output
1
P4₂
Output
1
P4₁
Output
1
P4₀
Output
1
Execution of BCLR Instruction
BCLR #0, @P4DDR ; Execute BCLR instruction on DDR
After Execution of BCLR Instruction
Input/output
DDR
P4₇
Output
1
P4₆
Output
1
P4₅
Output
1
P4₄
Output
1
P4₃
Output
1
P4₂
Output
1
P4₁
Output
1
P4₀
Input
0
Explanation: To execute the BCLR instruction, the CPU begins by reading P4DDR. Since
P4DDR is a write-only register, it is read as H'FF, even though its true value is H'3F.
Next the CPU clears bit 0 of the read data, changing the value to H'FE.
Finally, the CPU writes this value (H'FE) back to P4DDR to complete the BCLR instruction.
As a result, P4₀DDR is cleared to 0, making P4₀ an input pin. In addition, P4₇DDR and P4₆DDR
are set to 1, making P4₇ and P4₆ output pins.
The BCLR instruction can be used to clear flags in the on-chip registers to 0. In the case of the
IRQ status register (ISR), for example, a flag must be read as a condition for clearing it, but when
using the BCLR instruction, if it is known that a flag has been set to 1 in an interrupt-handling
routine, for instance, it is not necessary to read the flag ahead of time.
Rev.4.00 Aug. 20, 2007 Page 40 of 638
REJ09B0395-0400