HD6413008VF25 Datasheet, PDF (591/688 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Appendix B Internal I/O Registers
IER—IRQ Enable Register
Bit
7
6
⎯
⎯
Initial value
0
0
Read/Write R/W
R/W
H'EE015
Interrupt Controller
5
4
3
2
1
0
IRQ5E IRQ4E IRQ3E IRQ2E IRQ1E IRQ0E
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W R/W
IRQ5 to IRQ0 enable
0 IRQ5 to IRQ0 interrupts are disabled
1 IRQ5 to IRQ0 interrupts are enabled
ISR—IRQ Status Register
Bit
7
6
⎯
⎯
Initial value
0
0
Read/Write ⎯
⎯
H'EE016
Interrupt Controller
5
4
3
2
1
0
IRQ5F IRQ4F IRQ3F IRQ2F IRQ1F IRQ0F
0
0
0
0
0
0
R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)*
IRQ5 to IRQ0 flags
Bits 5 to 0
IRQ5F to IRQ0F
Setting and Clearing Conditions
[Clearing conditions]
• Read IRQnF when IRQnF = 1, then write 0 in IRQnF.
• IRQnSC = 0, IRQn input is high, and interrupt exception
0
handling is being carried out.
• IRQnSC = 1 and IRQn interrupt exception handling is being
carried out.
[Setting conditions]
1
• IRQnSC = 0 and IRQn input is low.
• IRQnSC = 1 and IRQn input changes from high to low.
Note: n = 5 to 0
Note: * Only 0 can be written to clear the flag.
Rev.4.00 Aug. 20, 2007 Page 545 of 638
REJ09B0395-0400