HD6413008VF25 Datasheet, PDF (144/688 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

5. Interrupt Controller
5.4.3 Interrupt Response Time
Table 5.5 indicates the interrupt response time from the occurrence of an interrupt request until the
first instruction of the interrupt service routine is executed.
Table 5.5 Interrupt Response Time
External Memory
No. Item
On-Chip
8-Bit Bus
Memory 2 States 3 States
16-Bit Bus
2 States 3 States
1 Interrupt priority
2*¹
2*¹
2*¹
decision
2*¹
2*¹
2 Maximum number
1 to 23 1 to 27
of states until end of
current instruction
1 to 31*⁴
1 to 23
1 to 25*⁴
3 Saving PC and CCR 4
8
12*⁴
4
6*⁴
to stack
4 Vector fetch
4
8
12*⁴
4
6*⁴
5 Instruction fetch*²
4
8
12*⁴
4
6*⁴
6 Internal processing*³ 4
4
4
4
4
Total
19 to 41 31 to 57 43 to 73
19 to 41 25 to 49
Notes: 1. 1 state for internal interrupts.
2. Prefetch after the interrupt is accepted and prefetch of the first instruction in the
interrupt service routine.
3. Internal processing after the interrupt is accepted and internal processing after vector
fetch.
4. The number of states increases if wait states are inserted in external memory access.
Rev.4.00 Aug. 20, 2007 Page 98 of 638
REJ09B0395-0400