HD6413008VF25 Datasheet, PDF (285/688 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

8. 16-Bit Timer
16-bit timer Operating Modes
Table 8.7 (a) 16-bit timer Operating Modes (Channel 0)
Register Settings
TSNC
TMDR
TIOR0
16TCR0
Operating Mode
Synchronous preset
PWM mode
Output compare A
Synchro-
nization MDF
SYNC0 = 1 ⎯
⎯
⎯
Output compare B
⎯
Input capture A
⎯
Input capture B
⎯
Counter By compare
clearing match/input
capture A
By compare
match/input
capture B
Syn-
chronous
clear
⎯
⎯
SYNC0 = 1 ⎯
FDIR PWM
⎯
⎯ PWM0 = 1
⎯ PWM0 = 0
⎯
⎯ PWM0 = 0
⎯ PWM0 = 0
⎯
Clear
Clock
IOA
IOB
Select
Select
⎯
*
IOA2 = 0
Other bits
unrestricted
IOB2 = 0
Other bits
unrestricted
IOA2 = 1
Other bits
unrestricted
IOB2 = 1
Other bits
unrestricted
CCLR1 = 0
CCLR0 = 1
⎯
CCLR1 = 1
CCLR0 = 0
⎯
CCLR1 = 1
CCLR0 = 1
Legend:
: Setting available (valid).
⎯: Setting does not affect this mode.
Note: * The input capture function cannot be used in PWM mode. If compare match A and compare match B
occur simultaneously, the compare match signal is inhibited.
Rev.4.00 Aug. 20, 2007 Page 239 of 638
REJ09B0395-0400