HD6413008VF25 Datasheet, PDF (490/688 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

16. RAM
16.1.1 Block Diagram
Figure 16.1 shows a block diagram of the on-chip RAM.
Internal data bus (upper 8 bits)
Internal data bus (lower 8 bits)
Bus interface
SYSCR
H'FEF20*
H'FEF22*
H'FEF21*
H'FEF23*
On-chip RAM
H'FFF1E*
H'FFF1F*
Even addresses
Legend:
SYSCR: System control register
Odd addresses
Note: * The lower 20 bits of the address are shown.
Figure 16.1 RAM Block Diagram
16.1.2 Register Configuration
The on-chip RAM is controlled by SYSCR. Table 16.2 gives the address and initial value of
SYSCR.
Table 16.2 System Control Register
Address*
Name
Abbreviation
H'EE012
System control register
SYSCR
Note: * Lower 20 bits of the address in advanced mode.
R/W
R/W
Initial Value
H'09
Rev.4.00 Aug. 20, 2007 Page 444 of 638
REJ09B0395-0400