HD6413008VF25 Datasheet, PDF (280/688 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

8. 16-Bit Timer
Contention between 16TCNT Write and Overflow or Underflow: If an overflow occurs in the
T₃ state of a 16TCNT write cycle, writing takes priority and the counter is not incremented. OVF
is set to 1.The same holds for underflow. See figure 8.41.
16TCNT write cycle
T₁
T₂
T₃
φ
Address bus
16TCNT address
Internal write signal
16TCNT input clock
Overflow signal
16TCNT
OVF
H'FFFF
M
16TCNT write data
Figure 8.41 Contention between 16TCNT Write and Overflow
Rev.4.00 Aug. 20, 2007 Page 234 of 638
REJ09B0395-0400