HD6413008VF25 Datasheet, PDF (276/688 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

8. 16-Bit Timer
8.6 Usage Notes
This section describes contention and other matters requiring special attention during 16-bit timer
operations.
Contention between 16TCNT Write and Clear: If a counter clear signal occurs in the T₃ state of
a 16TCNT write cycle, clearing of the counter takes priority and the write is not performed. See
figure 8.37.
16TCNT write cycle
T₁
T₂
T₃
φ
Address bus
16TCNT address
Internal write signal
Counter clear signal
16TCNT
N
H'0000
Figure 8.37 Contention between 16TCNT Write and Clear
Rev.4.00 Aug. 20, 2007 Page 230 of 638
REJ09B0395-0400